As at current, we see that CMOS technology is the driving technology of the microelectronics industry, and the conventional way of fabricating integrated circuits on bulk silicon substrates has illustrated problems such as unwanted parasitic effects, latchup, and the difficulty of making shallow junctions. In the recent years, the advent of Silicon-on-Insulator has proven superior in many aspects to their bulk counterparts, and the benefits include the absence of latch-up, the blocks play and learn reduced parasitic source and drain capacitances, the ease of making shallow junctions, radiation hardness, ability to operate at high temperature, improved transconductance and sharper subthreshold slope. There are several approaches available to create SOI wafers, and we discuss two particular techniques over here. First, we seek to illustrate a heteroepitaxy technique through the Ultra-Thin Silicon (UTSi) process where high quality Silicon-on-Sapphire (SOS) material is formed. Next, we look at a homoepitaxy technique called Epitaxial Lateral Overgrowth (ELO) technique which seeks to grow a homogenous crystal laterally on an insulator.

Ultra-Thin Silicon (UTSi) Process

Silicon-on-Sapphire (SOS) material was first introduced in 1964. SOS was recognized for its high speed and low power potential. The usage of Czochralski growth of sapphire crystals and the subsequent deposition of a silicon film in an epitaxial reactor had proved inefficient as there was high defect density due to lattice mismatch with defect densities near the Si-Sapphire interface reaching up to planar faults /cm and line defects/cm. This resulted in low resistivity, mobility, and lifetime near the interface. The silicon film deposited is also under compressive stress at room temperature due to different thermal expansion coefficients which may possibly result in relaxation in the film through crystallographic defects such as microtwins, stacking faults, and dislocations. Such consequences are undesired.

Hence, these reasons advocate the need for better heteroepitaxy technique, and in which the UTSi process is one such potential candidate. The steps involved in a UTSi process are as follows: See Figure 1.

Step 1: Grow a relatively thick film of silicon on sapphire. Silane (SiH4) is commonly used as the source of silicon for SOS growth. Its pyrolysis reaction in a carrier hydrogen gas, SiH4 –> Si + 2H2, results in the deposition of a silicon layer over the sapphire substrate. The deposition temperature is usually kept below 1050 deg C in order to prevent the autodeposition of aluminum from the sapphire substrate to the silicon layer. The desired silicon orientation is , which has been achieved on various sapphire orientations, i.e., , , .

Step 2: Implantation of Si into the silicon film is carried out to amorphize the bottom 2/3 of the silicon film, with the exception of a thin superficial layer, where the original defect density is the lowest.

Step 3: A low temperature thermal annealing step is then used to induce solid-phase regrowth of the amorphized silicon, using the top silicon layer as a seed.

Step 4: The silicon film is then thinned to the desired thickness by thermal oxidation, and the subsequent HF strip of the SiO. What remains is the final product of Silicon-on-Sapphire (SOS).

It has been demonstrated that UTSi process is capable of delivering relatively defect-free and stress free SOS material in which devices with a high effective mobility can be made.

Epitaxy on Silicon-On-Insulator Technology